1. Technical Field
Various embodiments generally relate to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus which includes a dummy memory cell block.
2. Related Art
In general, a semiconductor memory apparatus includes a memory bank for storing data. A plurality of bit lines and a plurality of word lines are disposed in the memory bank, and a plurality of memory cells are formed at points where the bit lines and the word lines cross each other. The plurality of memory cells may be electrically coupled with sense amplifiers through the bit lines. The data stored in the memory cells may be outputted or data may be written in the memory cells, through amplifying operations of the sense amplifiers.
FIG. 1 is a diagram showing the configuration of a conventional memory bank 10 having an open bit line structure. In FIG. 1, the memory bank 10 includes first to thirty second sub blocks SB0 to SB31, and bit line sense amplifier arrays (SA) 11 to 13 are disposed between the sub blocks. The bit line sense amplifier arrays 11 to 13 are shared by adjacent sub blocks. A plurality of bit lines BL and a plurality of word lines WLn, WL2n, WL3n and WL32n may be disposed in the respective sub blocks. The first sub block SB0 may share the bit line sense amplifier array 12 with the second sub block SB1, and the thirty first sub block SB30 may share the bit line sense amplifier array 13 with the thirty second sub block SB31. For example, one half of the bit lines BL which are disposed in the second sub block SB1 may be electrically coupled with the bit line sense amplifier array 12 which is shared by the previously adjacent first sub block SB0, and the other half of the bit lines BL may be electrically coupled with a bit line sense amplifier array which is shared by a next adjacent sub block (a third sub block, although not shown). Accordingly, one half of the bit lines may be amplified by the bit line sense amplifier array 12 by being paired with the bit lines disposed in the first sub block SB0, and the other half of the bit lines may be amplified by the bit line sense amplifier array by being paired with the bit lines disposed in the third sub block.
Although one half of the bit lines BL which are disposed in the first sub block SB0 is electrically coupled with the bit line sense amplifier array 12 which is shared by the second sub block SB1, the other half of the bit lines BL which are disposed in the first sub block SB0 are not used, which may be problematic. Also, although one half of the bit lines BL which are disposed in the thirty second sub block SB31 is electrically coupled with the bit line sense amplifier array 13 which is shared by the thirty first sub block SB30, memory cells which are electrically coupled with the other half of the bit lines BL are not used, which may be problematic. Therefore, the memory bank 10 may additionally include a dummy block DB. The dummy block DB may share the bit line sense amplifier array 11 with the first sub block SB0, and may provide bit lines to be sensed together with the bit lines BL which are disposed in the first sub block SB0. The other half of the bit lines of the dummy block DB may be electrically coupled with a bit line precharge voltage VBLP. Also, one half of the bit lines BL of the dummy block DB, which shares the bit line sense amplifier array 11 with the first sub block SB0, is configured to replace the other half of the bit lines BL of the thirty second sub block SB31. That is to say, the other half of the thirty second sub block SB31 and the one half of the dummy block DB may operate logically as the thirty second sub block SB31. Due to this fact, when writing data in the thirty second sub block SB31 or reading data from the thirty second sub block SB31, the word line WL32n of the thirty second sub block SB31 and the word line WL32n of the dummy block DB are simultaneously selected.